This paper presents experimental evidence suggesting that electromigration (EM) can be a serious reliability threat when the dimension of Cu interconnects approaches the nanoscale range. To understand the failure mechanism prevailing in nanoscale Cu interconnects, single-level, 400-[mu]m long interconnects with various effective widths, ranging from 750 nm to 80 nm, were made, EM tested, and characterized in this investigation. The results indicate that interface EM (Cu/barrier) may be the predominant EM mechanism in all line widths. The evidence supporting the active Cu/barrier interface EM includes the fact that the EM lifetime is inversely proportional to the interface area fraction. Microscopic analysis of the failure sites also supports the conclusion of interface EM because voids and hillocks are found at the ends of the test strip, which is not possible if lines fail by grain-boundary EM in the test structure used in this study. In addition, our study finds evidence that failure is assisted by a secondary mechanism. The influence of this factor is particularly significant when the feature size is small, resulting in more uniform distribution of failure time in narrower lines. Although limited, evidence suggests that the secondary factor is probably attributed to pre-existing defects or grain boundaries.

Key words: Electromigration, Cu interconnects, interface, diffusion barrier

INTRODUCTION

Reliability of Cu interconnects is a critical concern for the microelectronics industry, particularly with aggressive development toward 90-nm and 65-nm technology where the feature size of Cu interconnects is also in the nanoscale range. Such ultra-fine Cu interconnects are expected to be more prone to physical failures, not only because they are subjected to more strenuous use conditions, but also because the critical size for fatal defects, either as processed or developed, is smaller.1 All these conditions are especially problematic to electromigration (EM) reliability and are expected to pose significant technical challenges. Although much research attention has been directed toward reliability of Cu interconnects in general, few studies on EM reliability of nanometer-range interconnects have been published.2 Study of this subject is particularly important because recent studies, including our own, suggest that interface EM is likely to be the most active EM failure mechanism in Cu.3-9 With the decrease in feature size, interface area fraction inevitably increases, particularly in the case when the thickness is kept constant. With an increase in interface area fraction, ultra-fine Cu interconnects may suffer increasing EM damage.

One of the most important factors to consider in conducting an EM mechanism study is the selection of the test structure. The EM studies are often conducted with two-level structures where either drift kinetics or the reliability of the via can be measured. As vias are generally the weakest link, this is a practical structure for evaluating overall interconnect reliability. On the other hand, failure is forced to occur in or adjacent to the vias, and determination of the mechanism, for example, whether it is grain boundary or interface, is not straightforward. In addition, the influence of other factors, such as pre-existing defects, may be hidden and difficult to isolate from the primary mechanism. EM testing can also be done on a single-level structure. In this case, the results have less practical value; however, as the failure in a single-level structure is more sensitive to microstructural details, it is advantageous in investigating the failure mechanism and other factors that influence the mechanism. A few points of investigative focus when using a single-level interconnect are failure statistics, activation energy, current density exponent, and failure morphology. Among these, failure statistics and failure morphology are particularly useful because they reflect the interaction between the primary EM mechanism and microstructural details.

Because understanding of the EM failure mechanism in ultra-fine, damascene Cu interconnects is the prime objective, this investigation used a single-level structure and examined parameters indicative of the failure mechanism prevailing in Cu interconnects. For this, five line widths, 750-80 nm, have been subjected to accelerated EM testing. The results lead to two main conclusions. The first is that EM through the Cu interface is the primary EM mechanism. This conclusion is deduced from the fact that lifetime, measured by median time to failure (MTF), shows a linear dependence on the reciprocal of the interface area fraction. It is further substantiated by the fact that void and hillock formation is limited to the two ends of the test strip. The second conclusion is that there exists a secondary mechanism that further accelerates the failure. The exact nature of this acceleration factor is currently unknown; however, there are several indications that it is probably related to structural defects. These observations are summarized in this paper along with a brief discussion of their physical significance.